1. Technical Field of the Invention
The present invention relates to a logic device with reduced leakage current.
2. Description of Related Art
As the technology is shrinking, leakage current of devices is becoming a prime concern because it increases in the same order as that of active power. This increase in leakage is not only a concern in terms of higher power consumption but also for high performance memories as it affects bit line split.
FIG. 1 is a circuit diagram showing standby current components of a 6T SRAM cell. The cell comprises of transistors M11 to M16 with the interconnections as shown. The total leakage current is sum of the currents of M13, M12 and M16 and on state gate leakage of transistors M11 and M14 and accumulation mode gate leakage of transistor M15. Many efforts have been made to reduce leakage current. Some solutions use transistors with a high threshold voltage Vt for access while others make use of a dual threshold transistor.
Out of the many solutions offered, a solution to reduce leakage power is proposed by Kaushik Roy, Hai Li, “DRG-Cache: A Data Retention Gated ground Cache for Low Power” 2002 ACM 1-58113-461-Apr. 2, 2006 (the disclosure of which is hereby incorporated by reference). With reference to FIG. 2, which reproduces a circuit diagram, this article utilizes a gated ground NMOS transistor (20) between the ground GND and an array of SRAM cells (21). This NMOS transistor (20) is switched off during standby mode. This causes a significant increase in drain potential of the NMOS transistor (20) due to leakage.
FIG. 3 details another approach as mentioned in U.S. Pat. No. 6,314,041 (the disclosure of which is hereby incorporated by reference). In this approach, diodes M32 and M34 are connected to the memory column MC to provide limited supply in standby. This provides an alternative to the memory column for limiting voltage V intended for guaranteeing the operation of the memory column when transistors M31 and M33 are not active.
Respective diodes M32 and M34 connected in parallel with transistors M31 and M33, maintain steady state constant potential at virtual supply plane during standby state.
In the stand-by mode, if the equilibrium voltage across transistors M31 and M33 is smaller than the diode threshold voltage, the circuit operates in a normal operating mode. The transistors M31 and M33 are on and the column operates exactly like a conventional column in read/write modes. However, if the equilibrium voltage exceeds, for any reason, the diode threshold voltage, diodes M32 and M34 turn on. It is thus guaranteed that voltage V is never smaller than VDD minus twice the threshold voltage of a diode. Detailed working of this circuit can be obtained by reference to the referenced patent.
Current leakage is a function of variation in temperature and process. This leads to higher variation in virtual supply and virtual ground voltage as shown in FIG. 12. Particularly for a temperature variation of 25° C. to 125° C. leakage current of 100 nm transistor varies more than 100 times. This poses a serious problem on the methods discussed so far. Even with a diode connected scheme the variation in leakage, and hence the variation in noise margin, may lead to unacceptable levels. The size of the diode needed for an acceptable variation is high. With technology scaling, leakage reduction during active modes is also needed to be selectively applied in different portions of the core. Methods of leakage reduction should be tolerant to such conditions otherwise this may lead to a data integrity problem.
While the above-mentioned prior art solutions reduce leakage up to a certain extent, an extra NMOS/diode is needed for every 16 cells or for each memory column. Since the extra NMOS used is at the elementary level (one for 16 cells), the noise generated due to selection/deselection of NMOS affects the cell. Moreover, there is no escape for noise margin degradation with temperature variation.
All the techniques discussed so far were analyzed at deep-sub micron technology (sub-130 nm). Leakage current at these technology nodes has increased many fold. Particularly for systems on chip, excessive leakage may result in temperature rise and hence device failure. So a method is needed which reduces leakage when device is not operational as well as when the device is operational without the loss of reliability. In some cases at high temperatures, measures for leakage reduction are required.
A need exists in the art to provide an area efficient method of leakage reduction.
A need also exists in the art to provide a method to maintain virtual supply in range to provide sufficient noise margin.
A need further exists in the art to provide an area-effective overhead scheme in case of active constriction, also giving an edge over the leakage reduction.
A further need exists in the art to utilize the same size of NMOS for a bigger block of cells as active constriction is used.
There is also a need in the art to reduce impact of noise due to selection and deselection of transistors as constriction at the Global wordline level separates the NMOS/PMOS switch from the cell array.